The present embodiments relate to a method for fabricating a semiconductor device.
To form an open region such as a storage node hole and a contact hole in a semiconductor device, an insulation layer where the open region will be formed and an etch barrier pattern are formed in sequence. The insulation layer is then etched using the etch barrier pattern as an etch barrier to thereby form the open region. A conductive layer fills the open region to form a contact plug that electrically connects an underlying conductive layer to an overlying conductive layer. Alternatively, a conductive layer, a dielectric layer, and a conductive layer may be deposited into the open region in sequence to thereby form a metal-insulator-metal (MIM) capacitor having a cylindrical or concave structure.
As a design rule, as a semiconductor device gets smaller, the depth of the open region becomes deeper and a critical dimension (CD) of an open region becomes smaller. Accordingly, it is very difficult to stably form an open region with a high aspect ratio, for example, a plug hole for a metal contact (e.g., M1C) or a storage node hole of a cylindrical MIM capacitor.
FIG. 1 illustrates an open region of a typical semiconductor device wherein an open region 13 is formed in an insulation layer 12 formed on a substrate 11 including a predetermined structure. Region (A) illustrates a state in which the open region 13 is normally formed.
However, as illustrated in region (B), the typical semiconductor device has a limitation that a bottom CD W2 is smaller than a top CD W1 of the open region 13 (W1>W2). More specifically, although a dry etch is generally used to form the open region, the dry etch results in decreased etching efficiency as the open region 13 is etched deeper. This decreased efficiency is caused by a pressure inside the open region 13 that increases due to an etching gas and an etch by-product produced during the etching process. Such a decrease in the bottom CD W2 of the open region 13 leads to a leaning phenomenon of a storage node and a decrease in a preset capacitance of a capacitor in a semiconductor device. Furthermore, the decrease in the bottom CD W2 of the open region 13 causes a contact area of a contact plug with an underlying conductive layer to be reduced, thereby increasing a contact resistance there between.
Moreover, in line with the reduction in a design rule of a semiconductor device, a critical dimension of the open region 13 becomes smaller and a depth thereof becomes deeper. Accordingly, an etching margin for forming the open region 13 gradually decreases. This leads the bottom CD W2 to be much smaller than the top CD W1 in the open region 13, and as illustrated in the region (C) of FIG. 1, a contact-not-open phenomenon X also occurs.